The invention relates to digital circuit design.
Digital hardware designers lay out circuits to implement a given function. Often, it is desired to implement multiple copies of that function on a single integrated circuit (chip). While this can be accomplished by replicating the existing design multiple times, there are costs to that approach in terms of efficiency (as measured in area and power) and flexibility.
Particularly in the networking world where interfaces are frequently channelized (treated as multiple, separate, lower-speed interfaces), the ability to have a single chip which can carry out a task at a high rate, or which can carry out multiple copies of that task each at a lower rate, is desirable.
A method and system is shown for converting a digital circuit into a time division multiple access (TDMA) design. In one aspect of the invention, each flip flop included in the design is replaced with a scannable pipelined register (SPR) cell. In another aspect, each memory element (e.g., RAM) included in the design is replaced with a state saving device (e.g., TDMA RAM).
In one aspect, the invention provides a method for designing a digital circuit and includes identifying a single phase digital circuit implementing a desired function and operating at a first rate and determining a number of copies of the single phase digital circuit that are required for the digital circuit. Each copy of the single phase circuit is a phase and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The method includes identifying the state devices within the single phase digital circuit, replacing each state device in the single phase digital circuit with a multiphase state saving device and providing control signals to each multiphase state saving device to control the reading and writing of state information for each phase into and out of a respective multiphase state saving device.
Aspects of the invention can include one or more of the following features. The step of identifying the state devices can include identifying flip flops in the single phase digital circuit and the step of replacing each state device can include replacing each flip flop with a time division multiple access (TDMA) register cell. The step of replacing each flip flop with a TDMA register cell can include providing a state saving circuit for each phase and a phase multiplexor. Each state saving circuit can include a first multiplexor and a flip flop. The flip flop is operable to maintain state information for a given phase. The first multiplexor can be controlled by the control signals and operable to select from received data and an output of the flip flop whereby state information is maintained for each phase in a respective flip flop until a read time designated for a given phase. New data can be selectively written into a phase""s respective flip flop at a designated write time for the given phase. The phase multiplexor can receive as inputs the output from each flip flop. The phase multiplexor can be controlled by the control signals and is operable to read a respective phase""s data as stored in a respective flip flop in accordance with the read time for a given phase.
The method can further include determining if the digital circuit is to include a scanning input and output, and if so, the step of replacing can include replacing each flip flop with at least one scannable TDMA register cell. The step of replacing can further include providing second multiplexors for each phase. Each multiplexor can be controlled by a scanning control signal. The second multiplexors can be operable to select from the output of a flip flop of a respective phase or the output of a flip flop for a previous phase""s flip flop.
The step of replacing can include providing an output flip flop. The output flip flop can receive as an input data from the phase multiplexor and can be operable to provide state output for a respective phase clocked by a clocking signal. The step of identifying the state devices can include identifying random access memory (RAM) in the single phase digital circuit. The step of replacing each state device can include replacing each RAM with a time division multiple access RAM. The step of replacing each RAM can include adding copies of the RAM, one for each phase. The step of replacing each RAM can include replacing each RAM with a wider RAM configured to store all the state information for each phase in a portion of at least one wide address location. The step of replacing the RAM can include replacing each RAM with a deeper RAM where the deeper RAM includes addressable locations for storing state information for each phase.
In another aspect, the invention provides a method of converting a single phase circuit into a TDMA circuit and includes providing a single phase circuit, identifying the state devices within the single phase circuit and replacing each state device with a multiphase state saving device.
In another aspect, the invention provides a system including a logic circuit having state logic, wherein the state logic function is provided by a multiphase state saving circuit having a selectable output phase. The system includes logic circuitry to provide selection of the output phase.
Aspects of the invention can include one or more of the following features. The logic circuitry can include at least one TDMA cell or at least one SPR cell. The step of replacing the RAM can include providing control signals associated with the writing of data into a respective phase to provide the necessary extra state for the circuit. The step of replacing the RAM can include extending an address space of the RAM using control signals associated with the writing of data into a respective phase. The RAM can be a synchronous RAM and the step of replacing the RAM can include using control signals associated with the reading of data from and the writing of data to a respective phase to extend an address space of the RAM. The step of replacing the RAM can include using control signals associated with the writing of data to a respective phase to extend the address space of the synchronous RAM and a series of flip flops on an output of the synchronous RAM to time-align output data from the synchronous RAM.
In another aspect, the invention provides a system including a logic circuit having combinatorial and state logic. The logic circuit is selectively configurable as a single phase circuit or a multi-phase circuit. The single phase circuit implements a function and operates at a first rate. Each phase of the multi-phase circuit implements the function and operates at a lesser rate wherein the sum of the lesser rates is less than or equal to the first rate. The state logic function is provided by a multiphase state saving circuit having a selectable output phase such that the plural phases can be provided in the logic circuit without having to duplicate the combinatorial logic. The system includes logic circuitry to provide selection of the output phase.
Aspects of the invention may provide one or more of the following advantages. Designs incorporating the teaching of the present invention are easily reconfigurable to run in different modes: full or partial TDMA, or as a single copy. The resulting hardware minimizes the logic area and power required to implement multiple copies of the given function. For most designs, a quad TDMA (four-way) version of the design will increase the total area of the design by less than 50% (rather than the factor of four required if the design was simply replicated). In one practical case, that of an OC-192 RAC, a Quad TDMA design only increased area by just under 25%. The resulting hardware can be produced from an existing design with purely mechanical changes (replacing all the state elements in the design), and thus preserves the existing functionality.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.